1. Field of the Invention
The present invention relates to a multilayer ceramic capacitor and a process for preparing the same, and particularly to a multilayer ceramic capacitor that comprises an effective dielectric material section consisting of thin dielectric ceramic layers and internal electrode layers stacked alternately, and external cover dielectric layers that are stacked on the upper and lower surfaces of the effective dielectric material section for the protection thereof, and a process for preparing the same.
2. Description of Related Art
Recently, as electronic components become increasingly smaller in size and higher in functionality, efforts have been made to manufacture multilayer ceramic capacitors that are smaller in size and larger in capacity. Specifically, such multilayer ceramic capacitors have been manufactured as the dielectric ceramic layer thereof is made thinner to a thickness (distance between internal electrodes) of 10 μm or less and 100 or more internal electrode layers are stacked. With such a trend toward thinner dielectric ceramic layers, the mean grain size of main crystal phase that constitute the dielectric ceramic layers has been reduced to about 1 μm while particle size of the dielectric material powder and glass powder used to make it have been made smaller. Such technologies have been disclosed in, for example, Japanese Unexamined Patent Publication No. 10-241987 and Japanese Unexamined Patent Publication No. 9-97733.
However, in such a multilayer ceramic capacitor made by using dielectric material powder and glass powder of fine particles as described above, high shrinkage ratio of the dielectric material powder after firing causes the protective external cover dielectric layer 107 to shrink at a higher rate than the effective dielectric material section 105 that includes the dielectric ceramic layers 101 and the internal electrode layers 103. As a result, the external cover dielectric layer 107 tends to become smaller in size as shown in FIG. 3 (dimension of the external cover dielectric layer 107 before shrinkage is denoted as L1 and dimension thereof after shrinkage is denoted as L2). In such a multilayer ceramic capacitor, strain due to difference in shrinkage after firing has been causing cracks and/or delamination between the external cover dielectric layer and the effective dielectric material section and between the effective dielectric material sections.